https://github.com/jasonsu131/coe328-design-of-a-simple-general-purpose-processor
The designing of a simple general purpose processor using VHDL and Quartus II. Design consists of 2 latches, 4 seven segment displays, an arithmetic logic unit, a FSM, and a 4x16 decoder.
https://github.com/jasonsu131/coe328-design-of-a-simple-general-purpose-processor
cpu fpga quartus2 truthtable vhdl waveforms
Last synced: 2 months ago
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The designing of a simple general purpose processor using VHDL and Quartus II. Design consists of 2 latches, 4 seven segment displays, an arithmetic logic unit, a FSM, and a 4x16 decoder.
- Host: GitHub
- URL: https://github.com/jasonsu131/coe328-design-of-a-simple-general-purpose-processor
- Owner: jasonsu131
- Created: 2024-11-30T21:47:48.000Z (6 months ago)
- Default Branch: main
- Last Pushed: 2024-11-30T22:03:13.000Z (6 months ago)
- Last Synced: 2025-02-07T08:32:40.306Z (4 months ago)
- Topics: cpu, fpga, quartus2, truthtable, vhdl, waveforms
- Homepage:
- Size: 704 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
The Simple General-Purpose Processor designed consists of 2 latches, 4 seven segment displays, an arithmetic logic unit, a FSM, and a 4x16 decoder.
Each latch processes an 8-bit input (A and B) which represents the last four digits of our student number.
If the reset is not on, the 8-bit input is sent to the ALU through a positive edge clock input. The FSM is a moore machine that determines and switches to the next depending on the previous state.
There are a total of 9 states that switch through chronologically when data_in is on and the clock has a positive edge.
Each state has a corresponding student number digit which is sent to a seven segment display while the current state is passed onto the 4x16 decoder.
The 4x16 decoder is comprised of two 3x8 decoders and converts the 4-bit state inputs into 16-bit while the enable is on.
The ALU receives inputs A and B from the two latches, the state in 16-bit from the decoder, and a clock signal which is synchronous throughout the whole system.
The ALU performs a different calculation of A and B depending on the state, with the sign and upper and lower four bit results sent and displayed on a seven segment display.
Further component discriptions, waveforms, and truth tables are included in the lab report.