https://github.com/jbush001/risc-processor
32-bit RISC processor
https://github.com/jbush001/risc-processor
Last synced: 3 months ago
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32-bit RISC processor
- Host: GitHub
- URL: https://github.com/jbush001/risc-processor
- Owner: jbush001
- License: apache-2.0
- Created: 2012-02-05T17:16:14.000Z (over 13 years ago)
- Default Branch: master
- Last Pushed: 2019-01-07T07:17:01.000Z (almost 7 years ago)
- Last Synced: 2025-03-24T23:48:33.163Z (7 months ago)
- Language: Verilog
- Homepage:
- Size: 79.1 KB
- Stars: 22
- Watchers: 3
- Forks: 11
- Open Issues: 0
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Metadata Files:
- Readme: README
- License: LICENSE
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README
This is the first processor I designed, a 5 stage in-order MIPS-ish RISC. It features direct mapped L1 instruction and data caches, and branch prediction
The implementation is not very good, and is mostly preserved here for posterity. I made a number of mistakes in this design:
- The contents of the data cache are modeled as having a single read/write port. Because of the way tag lookup occurs, this means it can't perform a write immediately after a read because there is contention for the port. There is a bunch of logic in the issue stage to schedule around this condition.
- I started the design purely structural, which was unnecessary and harder to read.
- Many of the SRAMs are modeled as async read (including the register file). This precludes using the built-in block RAM resources, using more area, and slows down the max clock rate.