https://github.com/jc-ll/try_verilog
My humble trials using Verilog, coming from VHDL
https://github.com/jc-ll/try_verilog
Last synced: 9 months ago
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My humble trials using Verilog, coming from VHDL
- Host: GitHub
- URL: https://github.com/jc-ll/try_verilog
- Owner: JC-LL
- Created: 2020-06-24T14:32:47.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2020-06-24T15:07:38.000Z (over 5 years ago)
- Last Synced: 2025-04-02T08:14:12.805Z (9 months ago)
- Language: Verilog
- Size: 1.95 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# verilog_trials
My humble trials using Verilog, coming from VHDL