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https://github.com/jdah/jdh-8
An 8-bit minicomputer with a fully custom architecture
https://github.com/jdah/jdh-8
Last synced: 7 days ago
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An 8-bit minicomputer with a fully custom architecture
- Host: GitHub
- URL: https://github.com/jdah/jdh-8
- Owner: jdah
- License: mit
- Created: 2021-04-28T19:38:11.000Z (over 3 years ago)
- Default Branch: master
- Last Pushed: 2022-06-05T13:59:09.000Z (over 2 years ago)
- Last Synced: 2024-02-17T06:36:13.632Z (9 months ago)
- Language: C
- Size: 19.9 MB
- Stars: 1,252
- Watchers: 20
- Forks: 90
- Open Issues: 9
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# JDH-8
A fully custom 8-bit minicomputer with a unique architecture.
The program above is running in the emulator, see [`programs/pong.asm`](programs/pong.asm) for the source.
[See the video on the design](https://youtu.be/7A1SzIIKMho). \
[and the video on the build](https://youtu.be/vaGZapAGvwM).
## Machine Description
### Features
- 8-bit data width
- 16-bit address bus (64 KiB available memory + banking)
- 8 fully general purpose registers (5 normal + 2 indirect address + 1 flags)
- 16 instruction RISC architecture
- Port mapped I/O for device communication
### Instruction Set:
```
0: MW reg, imm8/reg -> reg = imm8/reg
1: LW reg, [HL/imm16] -> reg = [HL/imm16]
2: SW [HL/imm16], reg -> [HL/imm16] = reg
3: PUSH imm8/reg -> [SP--] = imm8/reg
4: POP reg -> reg = [++SP]
5: LDA [imm16] -> HL = imm16
6: JNZ imm8/reg -> imm8/reg != 0 ? PC = HL : NOP
7: INB reg, imm8/reg -> reg = PORT[imm8/reg]
8: OUTB imm8/reg, reg -> PORT[imm8/reg] = reg
9: ADD* reg, imm8/reg -> reg = reg + imm8/reg
A: ADC* reg, imm8/reg -> reg = reg + imm8/reg + c
B: AND reg, imm8/reg -> reg = reg & imm8/reg
C: OR reg, imm8/reg -> reg = reg | imm8/reg
D: NOR reg, imm8/reg -> reg = ~(reg | imm8/reg)
E: CMP* reg, imm8/reg -> f = compare reg, imm8/reg (see below)
F: SBB* reg, imm8/reg -> reg = reg - imm8/reg - b
*these instructions load the carry/borrow bits in the (F)lags register
```
### Registers
```
A (0): GP register/arg 0
B (1): GP register/arg 1
C (2): GP register/arg 2
D (3): GP register/arg 3
L (4): GP register/(L)ow index register
H (5): GP register/(H)igh index register
Z (6): GP register/return value
F (7): flags (LSB to MSB)
LESS
EQUAL
CARRY
BORROW
```
See [the spec](SPEC.txt) for more information.
## Schematic
The schematic requires a modified version of Logisim Evolution to view, [see here](https://github.com/jdah/logisim-evolution). You will need to build it from source.
## Toolchain
### Compiling on POSIX systems
Compile with `$ make`
### Compiling on Windows
1. Install MSYS2 (msys2.org)
2. Install MinGW-W64 from MSYS2
3. Get 64-bit SDL2 development tools (libsdl.org)
4. LIBPATH to your SDL location (`Makefile` automatically specifies C:/cdevlibs)
5. Change CC and LD to the location of GCC (including the executable name) in your MinGW-W64 install or add `gcc` and `ld` to PATH
6. Install xxd for Windows (https://sourceforge.net/projects/xxd-for-windows/)
7. Change variable XXD in `Makefile` to the location of XXD (including the executable name) or add `xxd` to PATH
8. Run mingw32-make inside project directory
### **Assembler** ([`asm`](./asm))
`./bin/asm [-h] [--help] [-v] [--verbose] [-n] [--no-builtin-macros] [-o file] file`
### **Emulator** ([`emu`](./emu))
`./bin/emu [-m/--mod module] [-r/--run] [-l/--load file address] [ROM file]`
#### Commands
- `SET `: set register data
- `GET `: get register value
- `PEEK
`: get memory value
- `POKE `: set memory data
- `INB `: get port data
- `OUTB `: write port data
- `STEP`: step one instruction
- `DUMP`: print current machine state
- `LOAD `: load ROM at address
- `MODS`: list modules
- `MOD `: load module
- `DEVICES`: list devices
- `RUN `: run at speed (hz) until halt
- `QUIT`: quit