https://github.com/jeasonstudio/ustb_fpga_experimentreport_pros

北京科技大学 数字逻辑 FPGA 实验报告及项目文件
https://github.com/jeasonstudio/ustb_fpga_experimentreport_pros

fpga ustb

Last synced: 4 months ago
JSON representation

北京科技大学 数字逻辑 FPGA 实验报告及项目文件

• Host: GitHub
• URL: https://github.com/jeasonstudio/ustb_fpga_experimentreport_pros
• Owner: jeasonstudio
• License: bsd-3-clause
• Created: 2017-04-19T15:45:38.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2017-06-04T13:35:33.000Z (over 8 years ago)
• Last Synced: 2025-05-20T10:09:15.807Z (5 months ago)
• Topics: fpga, ustb
• Language: Verilog
• Size: 35.2 MB
• Stars: 25
• Watchers: 2
• Forks: 4
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

          
# USTB_FPGA_ExperimentReport_Pros

北京科技大学 数字逻辑 FPGA 实验报告及项目文件