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https://github.com/jesseopdenbrouw/thuas-riscv

The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zba Zbs Sdext Sdtrig microcontroller
https://github.com/jesseopdenbrouw/thuas-riscv

fpga hardware riscv riscv32 riscv32im rv32im soc

Last synced: 1 day ago
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The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zba Zbs Sdext Sdtrig microcontroller

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README 

        
= The THUAS RISC-V 32-bit processor in VHDL



xref:docs/doc.adoc[Full Documentation]



A RISC-V 32-bit microcontroller written in VHDL targeted

for an FPGA.



== Quick info



This RISC-V microcontroller uses the RV32IM instruction set

and the Zicsr, Zicntr, Zicond, Zihpm, Zba, Zbs, Sdext and

Sdtrig extensions. The microcontroller is build around a

three-stage pipelined core.



All instructions from the "The RISC-V

Instruction Set Manual Volume I, Unprivileged Architecture,

Version 20240411", RV32, are supported. The instructions

from the M standard (hardware multiply/divide), RV32, are

supported. From the "The RISC-V Instruction Set Manual:

Volume II Privileged Architecture, Version 20240411", RV32,

`ECALL`, `EBREAK`, `MRET` and `WFI` are supported. The

microcontroller supports Machine mode only. Traps (interrupts

and exceptions) are supported.



Loads from memory require 3 clocks, stores require 2 clocks.

CSR operations require 1 clock. Multiplications require 3 clocks,

divides require 18 clocks. Jumps/branches taken require 3

clocks, the microcontroller does not support branch prediction.

All other instructions require 1 clock.



Current Coremark testbench shows a CPI of 1.73 and a score

of 1.93 coremark/MHz.



Software is written in C, ({cpp} is supported but there are

some limitations) and compiled using the RISC-V GNU C/{cpp}

compiler.



== Current flavor



The design is equipped with bootloader and on-chip debugger

hardware (both can be switched off). The bootloader can

be used without the on-chip debugger to upload executables

to the processor. The on-chip debugger can be used with

OpenOCD and GDB. It works with Eclipse CDT.

 

== Memory



The microcontroller uses FPGA onboard RAM blocks to emulate RAM

and program ROM. There is no support for cache or external RAM. Programs

are compiled with the GNU C compiler for RISC-V and the resulting

executable is transformed to a VHDL synthesizable ROM table.



* ROM: a ROM of 64 kB is available (placed in onboard RAM, may be extended).

* BOOT: a bootloader ROM of 4 kB (placed in onboard RAM).

* RAM: a RAM of 32 kB using onboard RAM block available (may be extended).

* I/O: a simple 32-bit input and 32-bit output is available, as

is a simple 7/8/9-bit UART with interrupt capabilities. Two SPI devices are

available, with one device used for SD card socket (DE0-CV board, no interrupt) and a

general purpose SPI device with hardware NSS. Two I2C devices are

available. A simple timer with interrupt is provided. A more elaborate

timer is included and can generate waveforms (Output Compare and PWM)

or count edges (Input Capture). A watchdog timer is available, it can

generate a system wide reset or an NMI. A machine mode software interrupt

is provided.

The external system timer MTIME is located in the I/O so it's memory mapped.



ROM starts at 0x00000000, BOOT (if available) starts at 0x10000000,

RAM starts at 0x20000000, I/O starts at 0xF0000000. May be changed

on 256 MB (top 4 bits) sections.



== CSR



A number of CSR registers are implemented: `time`, `timeh`, `[m]cycle`,

`[m]cycleh`, `[m]instret`, `[m]instreth`, `mvendorid`, `marchid`,

`mimpid`, `mhartid`, `mstatus`, `mstatush`, `misa`, `mie`, `mtvec`,

`mscratch`, `mepc`, `mcause`, `mip`, `mcountinhibit` as are the HPM

counters and event selectors. If on-chip debugging is enabled, the

`dcsr`, `dpc`, `tselect`, `tdata1`, `tdata2` and `tinfo` CSRs are available.

Some of these CSRs are hardwired. Others will be implemented when

needed. The `time` and `timeh` CSRs produces the time since reset

in microseconds, shadowed from the External Timer memory mapped

registers. Also two custom CSRs are implemented: `mxhw` which holds

information of included peripherals and `mxspeed` which contains

the synthesized clock speed.



== FPGA



The microcontroller is developed on a Cyclone V FPGA (5CEBA4F23C7)

with the use of the DE0-CV board by Terasic and Intel Quartus Prime

Lite 23.1. Simulation is possible with QuestaSim Intel Starter Edition.

You need a (free) license for that. The processor uses about

2900 ALM (cells) of 18480, depending on the settings. In the default

settings, ROM, BOOT, RAM and registers uses 43% of the available RAM blocks.



The design is also tested on a Digilent Arty S7/50 and a Cmod S7/25 (Spartan 7) board.



== Software



A number of C programs have been tested, created by the GNU C/{cpp} Compiler for

RISC-V. We tested the use of (software) floating point operations (both

float and double) and tested the mathematical library (sin, cos, et al.).

Traps (interrupts and exceptions) are tested and work.

Assembler programs can be compiled by the GNU assembler. We provide a CRT

(C startup) and linker file. {cpp} is supported but many language concepts

(e.g. cout with iostream) create a binary that is too big to fit in the

ROM.



We provide a basic set of systems call, trapped (ECALL) and non-trapped

(functions overriding the C library functions). Trapped system calls

are by default set up by the RISC-V C/{cpp} compiler, so no extra handling

is needed.



== On-chip debugger



The processor is equipped with an on-chip debugger that complies to the

RISC-V Debug Specification v1.0.0-rc3. It is an all-hardware solution,

there is no program buffer involved. All processor registers (including

CSRs) can be read and written (when possible). Memory can be read and

written. There is one hardware breakpoint available. De on-chip debugger

is compatible with OpenOCD and GDB. It can be used with Eclipse CDT. By

default, the on-chip debugger is disabled.



== Bootloader



By default, the design is equipped with a bootloader. When resetting the

FPGA, the bootloader waits about 5 seconds @50 MHz before the program

in the ROM is started. Using the bootloader, a program can written to

the ROM (see the documentation). The bootloader can also be used to

inspect the memory contents.



== Support for Windows tools



There is support for Windows tools. `srec2vhdl` and

`upload` can be build with GCC MinGW and Visual Studio.

For building the RISC-V programs, a RISC-V GNU GCC compiler

is needed.



Best is to use a precompiled compiler for Windows and

build tools (make, rm, mkdir etc.). Please have a look

at https://xpack.github.io/dev-tools/riscv-none-elf-gcc/[xPack RISC-V Toolchain]

and https://xpack.github.io/dev-tools/windows-build-tools/[xPack Windows Build Tools].

For building `srec2vhdl` and `upload`, you need a GCC native compiler. Have a look

at https://xpack.github.io/dev-tools/gcc/[The xPack GNU Compiler Collection (GCC)].

For on-chip debugging, see https://xpack-dev-tools.github.io/openocd-xpack/[xPack OpenOCD].



Take a short tour on xref:docs/xpack.adoc[Installing xPacks on Windows 11].



## Plans (or not) and issues



* We are *not* planning the C standard.

* Implement clock stretching and arbitration in the I2C1/I2C2 peripherals.

* Adding input synchronization for SPI1/SPI2 peripherals.

* Implement an I/O input/output multiplexer for GPIOA PIN and POUT. This will enable I/O functions to be multiplexed with normal port I/O.

* Test more functions of the standard and mathematical libraries.

* It is not possible to print `long long` (i.e. 64-bit) using `printf` et al. When using the format specifier `%lld`, `printf` just prints `ld`. This due to lack of support in the `nano` library.

* Adding Zbb extension.

* To start the pre-programmed bootloader, make sure the UART1 RxD pin is connected to a serial device OR make sure this pin is pulled high (DE0-CV board).



== Disclaimer



This microcontroller is for educational purposes only.

Work in progress. Things might change. Use with care.