https://github.com/jevinskie/aes-over-pcie
A VHDL implementation of 128 bit AES encryption with a PCIe interface.
https://github.com/jevinskie/aes-over-pcie
Last synced: 7 months ago
JSON representation
A VHDL implementation of 128 bit AES encryption with a PCIe interface.
- Host: GitHub
- URL: https://github.com/jevinskie/aes-over-pcie
- Owner: jevinskie
- License: bsd-3-clause
- Created: 2012-03-24T20:12:21.000Z (over 13 years ago)
- Default Branch: master
- Last Pushed: 2017-01-09T20:28:42.000Z (almost 9 years ago)
- Last Synced: 2025-03-27T09:11:58.316Z (7 months ago)
- Language: VHDL
- Homepage:
- Size: 36.8 MB
- Stars: 26
- Watchers: 5
- Forks: 10
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# aes-over-pcie
A VHDL implementation of 128 bit AES encryption with a PCIe interface.
The VHDL test benches were wired up to Python unit tests to verify the correct operation of the AES cipher.
The ASIC process we were targeting was not fast enough to keep up with line-speed PCIe serial data. Thus, the ASIC core integrates with a serial<>parallel PCIe bridge IC. The design was intended to be pipelined and parrallelized but that put it over our die size limit. The code is still there for that optimization, if you prefer to do so.
The S-box implemntation is compact and fast thanks to [the design](https://github.com/jevinskie/aes-over-pcie/blob/master/docs/aes/sbox1.pdf) by Edmin NC Mui.
This project was awarded the AMD Excellence in Design Award.