https://github.com/jevinskie/delta-debug-verilog-test

Delta Debugging for Verilog/SystemVerilog
https://github.com/jevinskie/delta-debug-verilog-test

Last synced: 4 months ago
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Delta Debugging for Verilog/SystemVerilog

• Host: GitHub
• URL: https://github.com/jevinskie/delta-debug-verilog-test
• Owner: jevinskie
• License: bsd-2-clause
• Created: 2022-12-16T18:55:42.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-12-16T21:30:04.000Z (almost 3 years ago)
• Last Synced: 2025-03-27T09:11:59.753Z (6 months ago)
• Language: Verilog
• Size: 155 KB
• Stars: 3
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# delta-debug-verilog-test

Delta Debugging for Verilog/SystemVerilog

Uses the exellent [picire](https://github.com/renatahodovan/picire) and

[picireny](https://github.com/renatahodovan/picireny) (grammar based picire)

Delta Debugging frameworks to reduce a Verilog/SystemVerilog test case down to a minimal interesting case.