https://github.com/jevinskie/mips--
A dual core MIPS subset CPU written in behavioral, synthesizable VHDL
https://github.com/jevinskie/mips--
Last synced: 6 months ago
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A dual core MIPS subset CPU written in behavioral, synthesizable VHDL
- Host: GitHub
- URL: https://github.com/jevinskie/mips--
- Owner: jevinskie
- Created: 2012-03-24T20:04:01.000Z (over 13 years ago)
- Default Branch: master
- Last Pushed: 2016-10-18T03:58:27.000Z (almost 9 years ago)
- Last Synced: 2025-03-27T09:12:04.764Z (7 months ago)
- Language: VHDL
- Homepage:
- Size: 363 KB
- Stars: 8
- Watchers: 2
- Forks: 4
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# mips--
A dual core MIPS subset CPU written in behavioral, synthesizable VHDL
MIPS-- is an implementation of a subset of MIPS in VHDL targeting a Altera DE2 development board. It was implemented in the [two process methodology described by Jiri Gaisler](http://www.gaisler.com/doc/vhdl2proc.pdf). The final implementation includes I-cache, D-cache, and dual cores with ll/sc synchronization instructions.
More information can be found in the [final report](final_report/final_report_jsweval.pdf).