https://github.com/jiegec/arty-a7-wm8731pmod
Example project for https://github.com/jiegec/WM8731PMOD
https://github.com/jiegec/arty-a7-wm8731pmod
Last synced: about 2 months ago
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Example project for https://github.com/jiegec/WM8731PMOD
- Host: GitHub
- URL: https://github.com/jiegec/arty-a7-wm8731pmod
- Owner: jiegec
- Created: 2021-03-17T14:04:05.000Z (about 4 years ago)
- Default Branch: master
- Last Pushed: 2023-05-09T08:27:34.000Z (about 2 years ago)
- Last Synced: 2025-02-07T09:45:49.123Z (3 months ago)
- Language: Tcl
- Homepage:
- Size: 9.04 MB
- Stars: 3
- Watchers: 3
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Arty-A7-WM8731PMOD
Sound is downloaded from [Wikimedia](https://commons.wikimedia.org/wiki/File:Ludwig_van_Beethoven_-_symphony_no._5_in_c_minor,_op._67_-_i._allegro_con_brio.ogg), which is public domain.
The design plays the first 2.5s of Beethovn Symphony No. 5 in C Minor Op. 67 repeatedly. Verified on WM8731PMOD 2021-03-09.
## Design
Main logic is in `src/hdl/top.v`. It contains logic for:
1. Generate clocks: LRCLK, MCLK, BCLK, I2C_SCL etc
2. Configure registers via i2c bus
3. Read pcm data from block ram
4. Output audio via i2s interface