https://github.com/jiegec/chisel-memory-lower

Lower chisel memories to SRAM macros
https://github.com/jiegec/chisel-memory-lower

Last synced: 2 months ago
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Lower chisel memories to SRAM macros

• Host: GitHub
• URL: https://github.com/jiegec/chisel-memory-lower
• Owner: jiegec
• License: mit
• Created: 2023-04-05T00:49:22.000Z (almost 2 years ago)
• Default Branch: master
• Last Pushed: 2024-03-25T05:33:11.000Z (10 months ago)
• Last Synced: 2024-10-26T22:48:48.040Z (3 months ago)
• Language: Python
• Homepage:
• Size: 78.1 KB
• Stars: 9
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# chisel-memory-lower

Lower chisel3 memory Blackbox to macros.

Targets:

- Xilinx

- ARM Memory IP

Usage:

```shell

python3 -m chisel_memory_lower.generate xilinx example.conf --tb

python3 -m chisel_memory_lower.generate arm example.conf --arm-config arm.yaml --tb

```

## Read under Write

Chisel allows three read under write behaviors, `Undefined`, `ReadFirst` or `WriteFirst`. For 1R1W RAM, The behavior is:

- `SyncReadMem()`: unspecified in FIRRTL, `WriteFirst` in behavior model

- `SyncReadMem(Undefined)`: unspecified in FIRRTL, `WriteFirst` in behavior model

- `SyncReadMem(ReadFirst)`: `old` in FIRRTL, `ReadFirst` in behavior model

- `SyncReadMem(WriteFirst)`: `new` in FIRRTL, `WriteFirst` in behavior model

However, XPM only supports `Undefined`(NO_CHANGE & WRITE_FIRST, generates `x`) and `ReadFirst`(READ_FIRST). ARM Memory IP only supports `Undefined`(generates `x`). Thus the behavior is not guaranteed when lowering.