https://github.com/jiegec/usbh
https://github.com/jiegec/usbh
Last synced: over 1 year ago
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- Host: GitHub
- URL: https://github.com/jiegec/usbh
- Owner: jiegec
- Created: 2019-07-21T11:04:53.000Z (about 7 years ago)
- Default Branch: master
- Last Pushed: 2019-07-25T02:36:51.000Z (almost 7 years ago)
- Last Synced: 2025-03-28T20:45:57.159Z (over 1 year ago)
- Language: Coq
- Size: 46.9 KB
- Stars: 3
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# USB1.1 Host Controller packaged for Xilinx IP
This is a fork of [core_usb_host](https://github.com/ultraembedded/core_usb_host), with some customizations and fixes.
## Differences between this and upstream repo
1. AXI4-Lite address and data no longer need to arrive in the same cycle
2. Support 60MHz utmi clock instead of 48MHz
3. Fix RX and TX IFS logic where IFS should be counted after EOP is sent by PHY
4. Add new CTRL2 register(address 0x24) to control phy reset
5. Use XPM FIFO to match timing requirements, thus only Xilinx Vivado is supported now
## License
Licensed under GPLv3.