https://github.com/jiegec/verilog-format

A naive verilog/systemverilog formatter
https://github.com/jiegec/verilog-format

Last synced: 6 months ago
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A naive verilog/systemverilog formatter

• Host: GitHub
• URL: https://github.com/jiegec/verilog-format
• Owner: jiegec
• License: mit
• Created: 2019-09-19T00:57:43.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2025-03-22T11:49:55.000Z (over 1 year ago)
• Last Synced: 2025-04-01T15:42:36.524Z (over 1 year ago)
• Language: SystemVerilog
• Homepage:
• Size: 80.1 KB
• Stars: 20
• Watchers: 2
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# verilog-format

A naive verilog/systemverilog formatter. Works on tokens instead of AST with minimal lexical analysis.

## Usage

`verilog-format --file `

It will print the formatted file to stdout.

## License

Licensed under MIT license.