https://github.com/jiegec/verilog-lang

A hand-written recursive decent Verilog parser.
https://github.com/jiegec/verilog-lang

rust verilog

Last synced: over 1 year ago
JSON representation

A hand-written recursive decent Verilog parser.

• Host: GitHub
• URL: https://github.com/jiegec/verilog-lang
• Owner: jiegec
• License: mit
• Created: 2020-03-02T09:12:28.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2022-09-18T12:29:19.000Z (almost 4 years ago)
• Last Synced: 2025-04-01T16:55:58.113Z (over 1 year ago)
• Topics: rust, verilog
• Language: Rust
• Homepage:
• Size: 154 KB
• Stars: 11
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

          
# verilog-lang

[![Coverage Status](https://coveralls.io/repos/github/jiegec/verilog-lang/badge.svg?branch=master)](https://coveralls.io/github/jiegec/verilog-lang?branch=master)

An incomplete Verilog(with part of SystemVerilog) parser.