https://github.com/jiegec/verilog-lang

A hand-written recursive decent Verilog parser.
https://github.com/jiegec/verilog-lang

rust verilog

Last synced: 2 months ago
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A hand-written recursive decent Verilog parser.

• Host: GitHub
• URL: https://github.com/jiegec/verilog-lang
• Owner: jiegec
• License: mit
• Created: 2020-03-02T09:12:28.000Z (almost 5 years ago)
• Default Branch: master
• Last Pushed: 2022-09-18T12:29:19.000Z (over 2 years ago)
• Last Synced: 2024-10-26T22:48:41.117Z (3 months ago)
• Topics: rust, verilog
• Language: Rust
• Homepage:
• Size: 154 KB
• Stars: 11
• Watchers: 3
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# verilog-lang

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An incomplete Verilog(with part of SystemVerilog) parser.