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https://github.com/jminjares4/digital-system-2

Digital System 2 Lab
https://github.com/jminjares4/digital-system-2

digital-design verilog

Last synced: 15 days ago
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Digital System 2 Lab

Host: GitHub
URL: https://github.com/jminjares4/digital-system-2
Owner: jminjares4
Created: 2022-01-18T21:20:26.000Z (about 3 years ago)
Default Branch: main
Last Pushed: 2022-03-31T18:59:13.000Z (almost 3 years ago)
Last Synced: 2024-11-11T15:43:40.452Z (2 months ago)
Topics: digital-design, verilog
Language: Verilog
Homepage:
Size: 5.89 MB
Stars: 0
Watchers: 1
Forks: 0
Open Issues: 0
Metadata Files:
- Readme: README.md

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README

        # Digital-System-2

This repository will contain the lab for Digital System 2. The lab will be developed using `Verilog` and `Xilinx Vivado`.

# Table of Content

1) [Lab 1  XOR implemented with NAND gates](https://github.com/jminjares4/Digital-System-2/tree/main/Lab%201)

2) [Lab 2 Hexadecimal Full Adder](https://github.com/jminjares4/Digital-System-2/tree/main/Lab%202)

3) [Lab 3 ASM implementation using Xilinx ISE HAWK](https://github.com/jminjares4/Digital-System-2/tree/main/Lab%203)

## Author:

* [**Jesus Minjares**](https://github.com/jminjares4)


  * Master of Science in Computer Engineering


[![Outlook](https://img.shields.io/badge/Microsoft_Outlook-0078D4?style=for-the-badge&logo=microsoft-outlook&logoColor=white&style=flat)](mailto:[email protected]) 

[![LinkedIn](https://img.shields.io/badge/LinkedIn-0077B5?style=for-the-badge&logo=linkedin&logoColor=white&style=flat)](https://www.linkedin.com/in/jesus-minjares-157a21195/) [![GitHub](https://img.shields.io/badge/GitHub-100000?style=for-the-badge&logo=github&logoColor=white&style=flat)](https://github.com/jminjares4)