https://github.com/jmitchell/arm-iss

(pre-alpha) Instruction set simulator for the ARM architecture
https://github.com/jmitchell/arm-iss

Last synced: about 1 month ago
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(pre-alpha) Instruction set simulator for the ARM architecture

• Host: GitHub
• URL: https://github.com/jmitchell/arm-iss
• Owner: jmitchell
• License: gpl-3.0
• Created: 2015-07-19T06:38:00.000Z (over 9 years ago)
• Default Branch: master
• Last Pushed: 2015-07-28T17:01:55.000Z (over 9 years ago)
• Last Synced: 2023-04-07T21:37:31.512Z (over 1 year ago)
• Language: Common Lisp
• Homepage:
• Size: 160 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 1
• Metadata Files:
  • Readme: README.txt
  • License: COPYING

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README

        
arm-iss

=======

arm-iss is in the planning/prototyping phase. Seriously, don't even

think about touching it yet...

Goals

-----

* Implement an instruction set simulator for ARM.

* Develop small, modular components and test them in isolation.

  * For example, the ALU only needs access to the register file and

    barrel shifter output to produce meaningful results. However, it

    doesn't need direct access to RAM.

* Favor fundamental features over exhaustive coverage and extensive

  validation.

  * Defer interrupts, exceptions, and mode switching until the basics

    work in USR mode.

  * Focus on ARM rather than Thumb state.

  * Keep the memory and bus architecture as simple as possible to

    demonstrate the chip's core behaves as expected.

* Aim for portability, supporting a variety of hardware architectures,

  operating systems, and Common Lisp implementations.

Running tests

-------------

    (push #p"./" asdf:*central-registry*)

    (ql:quickload "arm-iss/test")

    (arm-iss-test:run-tests)