https://github.com/jn513/estudos_verilog

Exemplos feito em verilog para estudos
https://github.com/jn513/estudos_verilog

fpga fpga-programming hardware verilog verilog-code verilog-hdl

Last synced: 7 months ago
JSON representation

Exemplos feito em verilog para estudos

• Host: GitHub
• URL: https://github.com/jn513/estudos_verilog
• Owner: JN513
• License: mit
• Created: 2023-10-08T17:18:33.000Z (about 2 years ago)
• Default Branch: main
• Last Pushed: 2024-04-01T21:19:36.000Z (over 1 year ago)
• Last Synced: 2025-02-08T11:43:11.379Z (9 months ago)
• Topics: fpga, fpga-programming, hardware, verilog, verilog-code, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 10.6 MB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

          
# Estudos Verilog