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https://github.com/jn513/risco-5s
RISC-V Simulator with RV32IM implementation, built during a few days off.
https://github.com/jn513/risco-5s
riscv riscv-assembly riscv-emulator riscv-simulator riscv32 riscv32i
Last synced: 8 days ago
JSON representation
RISC-V Simulator with RV32IM implementation, built during a few days off.
- Host: GitHub
- URL: https://github.com/jn513/risco-5s
- Owner: JN513
- License: mit
- Created: 2024-08-05T22:46:01.000Z (5 months ago)
- Default Branch: main
- Last Pushed: 2024-10-27T21:06:03.000Z (about 2 months ago)
- Last Synced: 2024-10-28T01:08:14.471Z (about 2 months ago)
- Topics: riscv, riscv-assembly, riscv-emulator, riscv-simulator, riscv32, riscv32i
- Language: C
- Homepage: https://jn513.github.io/Risco-5S/
- Size: 648 KB
- Stars: 3
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- Contributing: CONTRIBUTING.md
- Funding: .github/FUNDING.yml
- License: LICENSE
Awesome Lists containing this project
README
# Risco-5S
Simulador RISCV capaz de executar as instrucões do conjunto RV32IM