https://github.com/jrmoulton/sevensegmentimage

Verilog implementation for a 7 segment display on a basys3board
https://github.com/jrmoulton/sevensegmentimage

Last synced: 6 days ago
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Verilog implementation for a 7 segment display on a basys3board

• Host: GitHub
• URL: https://github.com/jrmoulton/sevensegmentimage
• Owner: jrmoulton
• Created: 2021-09-23T18:11:07.000Z (over 3 years ago)
• Default Branch: master
• Last Pushed: 2021-10-05T03:23:34.000Z (over 3 years ago)
• Last Synced: 2025-01-12T01:05:03.013Z (14 days ago)
• Language: Verilog
• Size: 505 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Seven Segment Image

Verilog implementation for a 7 segment display on a basys3 board

This project implements several forms of verilog code in order to generate numbers 1-9 and A-F on a seven segment display. 

The organization in vivado is likely terrible but in a few moments the project structure can be changed so that the project is implemented with either heirarachal or with combinational code.