https://github.com/jrmoulton/simple-alu

A calculator in Verilog for the Basys3 FPGA
https://github.com/jrmoulton/simple-alu

Last synced: about 2 months ago
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A calculator in Verilog for the Basys3 FPGA

• Host: GitHub
• URL: https://github.com/jrmoulton/simple-alu
• Owner: jrmoulton
• Created: 2021-12-10T02:36:58.000Z (about 3 years ago)
• Default Branch: main
• Last Pushed: 2021-12-10T02:50:49.000Z (about 3 years ago)
• Last Synced: 2023-03-02T15:37:30.725Z (almost 2 years ago)
• Language: Verilog
• Size: 8.79 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0

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