https://github.com/jrmoulton/verilog-mux

A 2-1 mux in verilog with assign statements
https://github.com/jrmoulton/verilog-mux

Last synced: about 2 months ago
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A 2-1 mux in verilog with assign statements

• Host: GitHub
• URL: https://github.com/jrmoulton/verilog-mux
• Owner: jrmoulton
• Created: 2021-10-07T18:29:30.000Z (over 3 years ago)
• Default Branch: main
• Last Pushed: 2021-10-21T15:53:08.000Z (about 3 years ago)
• Last Synced: 2023-03-02T15:37:32.069Z (almost 2 years ago)
• Language: Verilog
• Size: 5.86 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0

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