https://github.com/jserv/rv32jit

JIT-accelerated RISC-V instruction set simulator
https://github.com/jserv/rv32jit

dynamic-binary-translation jit-compiler risc-v riscv riscv-emulator riscv-simulator riscv32

Last synced: 3 days ago
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JIT-accelerated RISC-V instruction set simulator

• Host: GitHub
• URL: https://github.com/jserv/rv32jit
• Owner: jserv
• License: mit
• Created: 2023-10-02T20:00:23.000Z (about 1 year ago)
• Default Branch: master
• Last Pushed: 2023-12-07T08:39:13.000Z (11 months ago)
• Last Synced: 2024-04-20T01:42:19.219Z (7 months ago)
• Topics: dynamic-binary-translation, jit-compiler, risc-v, riscv, riscv-emulator, riscv-simulator, riscv32
• Language: C++
• Homepage:
• Size: 171 KB
• Stars: 28
• Watchers: 4
• Forks: 7
• Open Issues: 2
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# rv32jit

`rv32jit` is a modern C++-based RISC-V instruction set simulator with a JIT

assembler serving as an x86-64 binary translator.

Features

* Fast runtime for executing the RV32 ISA

* Built-in ELF loader

* Implementation of partial Linux system calls

## Build and Verify

Currently, only GNU/Linux is supported for building `rv32jit`.

`rv32jit` relies on specific third-party packages for full functionality.

Please install the following package in advance.

* clang version 15+, which can be downloaded from the [LLVM Page](https://releases.llvm.org/download.html).

* `libelf-dev`

Build the simulator:

```shell

$ make

```

You might receive the message "Please run 'make' again."

If you do, simply follow the instruction and run `make` once more.

Download prebuilt RISC-V ELF files and run:

```shell

$ make check

```

## License

`rv32jit` is available under a permissive MIT-style license.

Use of this source code is governed by a MIT license that can be found in the [LICENSE](LICENSE) file.