https://github.com/juniper/simple_reg_model

System verilog register model for uvm testbenches.
https://github.com/juniper/simple_reg_model

Last synced: about 1 year ago
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System verilog register model for uvm testbenches.

• Host: GitHub
• URL: https://github.com/juniper/simple_reg_model
• Owner: Juniper
• License: mit
• Created: 2017-08-03T14:35:48.000Z (almost 9 years ago)
• Default Branch: master
• Last Pushed: 2018-08-29T13:21:33.000Z (almost 8 years ago)
• Last Synced: 2023-03-11T00:53:12.760Z (over 3 years ago)
• Language: Perl
• Size: 14.4 MB
• Stars: 19
• Watchers: 14
• Forks: 13
• Open Issues: 1

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