https://github.com/kaleid-liner/fpga-tetris

Tetris based on Nexys4 DDR FPGA Board
https://github.com/kaleid-liner/fpga-tetris

fpga tetris verilog

Last synced: 25 days ago
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Tetris based on Nexys4 DDR FPGA Board

• Host: GitHub
• URL: https://github.com/kaleid-liner/fpga-tetris
• Owner: kaleid-liner
• Created: 2018-12-10T12:14:59.000Z (about 6 years ago)
• Default Branch: master
• Last Pushed: 2018-12-14T11:13:27.000Z (about 6 years ago)
• Last Synced: 2024-11-15T17:30:07.609Z (3 months ago)
• Topics: fpga, tetris, verilog
• Language: SystemVerilog
• Size: 2.09 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:

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