https://github.com/kar-dim/icsd-digitalsystems

Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).
https://github.com/kar-dim/icsd-digitalsystems

verilog

Last synced: 5 days ago
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Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).

• Host: GitHub
• URL: https://github.com/kar-dim/icsd-digitalsystems
• Owner: kar-dim
• Created: 2024-08-09T18:05:43.000Z (5 months ago)
• Default Branch: master
• Last Pushed: 2024-10-16T21:00:03.000Z (3 months ago)
• Last Synced: 2024-10-18T20:32:03.250Z (3 months ago)
• Topics: verilog
• Language: VHDL
• Homepage:
• Size: 20.4 MB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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# ICSD-DigitalSystems

Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).