https://github.com/kenny2github/verilog-cpu

A very rudimentary and haphazard CPU created in Verilog.
https://github.com/kenny2github/verilog-cpu

cpu verilog verilog-hdl

Last synced: 3 days ago
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A very rudimentary and haphazard CPU created in Verilog.

• Host: GitHub
• URL: https://github.com/kenny2github/verilog-cpu
• Owner: Kenny2github
• License: mit
• Created: 2022-12-11T04:13:31.000Z (almost 2 years ago)
• Default Branch: main
• Last Pushed: 2022-12-15T22:37:07.000Z (almost 2 years ago)
• Last Synced: 2024-10-17T06:51:36.928Z (19 days ago)
• Topics: cpu, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 78.1 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# verilog-cpu

A very rudimentary and haphazard CPU created in Verilog (not SV!).

Consider this a perpetual work-in-progress.