https://github.com/kevinkit/esr

Project in VHDL for inteconnecting several prozessor
https://github.com/kevinkit/esr

Last synced: 3 days ago
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Project in VHDL for inteconnecting several prozessor

• Host: GitHub
• URL: https://github.com/kevinkit/esr
• Owner: kevinkit
• Created: 2016-05-26T19:17:23.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2016-10-19T12:49:54.000Z (over 8 years ago)
• Last Synced: 2024-11-23T10:41:31.444Z (2 months ago)
• Language: VHDL
• Size: 33.2 KB
• Stars: 0
• Watchers: 1
• Forks: 1
• Open Issues: 0

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