https://github.com/khushhallchandra/simulated-annealing
Simulated Annealing to minimize the wirelength
https://github.com/khushhallchandra/simulated-annealing
cad ee677 iitb python simulated-annealing vlsi
Last synced: 16 days ago
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Simulated Annealing to minimize the wirelength
- Host: GitHub
- URL: https://github.com/khushhallchandra/simulated-annealing
- Owner: khushhallchandra
- License: mit
- Created: 2016-10-05T17:03:57.000Z (about 9 years ago)
- Default Branch: master
- Last Pushed: 2017-02-23T19:50:12.000Z (over 8 years ago)
- Last Synced: 2023-02-27T19:30:41.958Z (over 2 years ago)
- Topics: cad, ee677, iitb, python, simulated-annealing, vlsi
- Language: Python
- Size: 698 KB
- Stars: 9
- Watchers: 2
- Forks: 3
- Open Issues: 0