https://github.com/kigawas/mipscpu

A single cycle CPU running on Xilinx Spartan 6 XC6LX16-CS324, supporting 31 MIPS instructions.
https://github.com/kigawas/mipscpu

educational-project mips verilog

Last synced: 26 days ago
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A single cycle CPU running on Xilinx Spartan 6 XC6LX16-CS324, supporting 31 MIPS instructions.

• Host: GitHub
• URL: https://github.com/kigawas/mipscpu
• Owner: kigawas
• License: apache-2.0
• Created: 2015-01-03T01:18:17.000Z (about 10 years ago)
• Default Branch: master
• Last Pushed: 2020-03-09T12:20:03.000Z (almost 5 years ago)
• Last Synced: 2024-11-12T00:42:43.963Z (3 months ago)
• Topics: educational-project, mips, verilog
• Language: Verilog
• Homepage:
• Size: 17.6 KB
• Stars: 2
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
MipsCPU

=======

A single cycle CPU running on Xilinx Spartan-6 XC6LX16-CS324, supporting 31 MIPS instructions.

>*  31 MIPS instructions.

>*  Single Cycle, without interruptions and exceptions(maybe add these features later).

Instructions:

>*  ``R-Type: ADD, ADDU, SUB, SUBU, AND, OR, XOR, NOR, SLT, SLTU, SLL, SLLV, SRL, SRLV, SRA, SRAV, JR``

>*  ``I-Type: ADDI, ADDIU, ANDI, ORI, XORI, LW, SW, BEQ, BNE, SLTI, SLTIU, LUI``

>*  ``J-Type: J, JAL``

MIPS Instruction specifications:

[MIPS32 Architecture for Programmers(English, PDF Format)](http://mips246.tongji.edu.cn/file/reference/MIPS32%E6%8C%87%E4%BB%A4%E9%9B%86.pdf)

FPGA Information:

[Xilinx Spartan-6 XC6LX16-CS324](http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3&CFID=7134617&CFTOKEN=119ce24510883320-C6FCB8D8-5056-0201-02E1008C8300EA55)