https://github.com/kitsunesemcalda/trabalho-pratico-circuitos-digitais
Creating a Implementation about estelar simulator in Verilog
https://github.com/kitsunesemcalda/trabalho-pratico-circuitos-digitais
fpga fpga-programming max10-lite star star-simulation
Last synced: 25 days ago
JSON representation
Creating a Implementation about estelar simulator in Verilog
- Host: GitHub
- URL: https://github.com/kitsunesemcalda/trabalho-pratico-circuitos-digitais
- Owner: KitsuneSemCalda
- License: mit
- Created: 2023-07-24T22:10:33.000Z (almost 2 years ago)
- Default Branch: master
- Last Pushed: 2023-08-03T22:03:37.000Z (over 1 year ago)
- Last Synced: 2023-08-03T23:24:13.812Z (over 1 year ago)
- Topics: fpga, fpga-programming, max10-lite, star, star-simulation
- Language: Tcl
- Homepage:
- Size: 15.2 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- License: LICENSE