https://github.com/klauer/simple_scaler

Papilio Pro FPGA board-based 16 channel, 32-bit simple LVTTL scaler
https://github.com/klauer/simple_scaler

Last synced: 3 months ago
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Papilio Pro FPGA board-based 16 channel, 32-bit simple LVTTL scaler

• Host: GitHub
• URL: https://github.com/klauer/simple_scaler
• Owner: klauer
• Created: 2014-04-01T15:06:52.000Z (about 11 years ago)
• Default Branch: master
• Last Pushed: 2014-04-01T15:24:42.000Z (about 11 years ago)
• Last Synced: 2025-01-17T16:51:49.603Z (5 months ago)
• Language: VHDL
• Size: 141 KB
• Stars: 0
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
Simple scaler

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A Papilio Pro FPGA board-based 16 channel, 32-bit simple LVTTL scaler

Written in VHDL, tested under Xilinx ISE 14.7

Notes

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Scaler = pulse counter

Simple scaler means there are no options -- 1 second count rate and that's it.