https://github.com/klus3kk/vitesse

Simple 16-bit RISC processor project, designed and implemented using VHDL.
https://github.com/klus3kk/vitesse

Last synced: about 13 hours ago
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Simple 16-bit RISC processor project, designed and implemented using VHDL.

• Host: GitHub
• URL: https://github.com/klus3kk/vitesse
• Owner: Klus3kk
• Created: 2024-03-18T12:50:05.000Z (10 months ago)
• Default Branch: main
• Last Pushed: 2024-11-19T20:19:24.000Z (about 2 months ago)
• Last Synced: 2024-11-19T20:22:27.124Z (about 2 months ago)
• Language: VHDL
• Homepage:
• Size: 11.7 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# **Vitesse**  

**Vitesse** is a 16-bit RISC (Reduced Instruction Set Computer) processor, implemented using **VHDL (VHSIC Hardware Description Language)**. Designed with simplicity and educational value in mind, it focuses on executing fundamental arithmetic and logical operations efficiently.

## **Features**:

- **16-bit ALU (Arithmetic Logic Unit):** Performs core arithmetic operations (addition, subtraction) and logical operations (AND, OR, NOT).  

- **Simple Instruction Set Architecture (ISA):** Features a streamlined set of instructions for arithmetic, logic, and data movement.  

- **Register File:** Includes a small set of general-purpose registers (e.g., 8 registers).  

- **Program Counter (PC):** Tracks the address of the next instruction to be executed.  

- **Control Unit:** Decodes instructions and orchestrates control signals for the processor’s components.  

- **Memory Interface:** Provides connectivity to a basic RAM model for instruction and data storage.  

- **Single-Cycle Execution:** Executes one instruction per clock cycle for simplicity.

## **Technologies**:

- **VHDL:** Hardware description language for processor implementation.  

- **GHDL:** Open-source simulator for testing and debugging VHDL designs.

**Status:** *In progress*