https://github.com/krutideepanpanda/risc-v-based-micro-controller-using-openlane

This is part of EC383 - Mini Project in VLSI Design.
https://github.com/krutideepanpanda/risc-v-based-micro-controller-using-openlane

openlane openlane-flow verilog verilog-processor verilog-project vlsi vlsi-design

Last synced: 2 days ago
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This is part of EC383 - Mini Project in VLSI Design.

• Host: GitHub
• URL: https://github.com/krutideepanpanda/risc-v-based-micro-controller-using-openlane
• Owner: krutideepanpanda
• License: mit
• Created: 2022-03-03T12:59:34.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2022-05-08T07:11:53.000Z (almost 3 years ago)
• Last Synced: 2024-12-04T05:22:36.912Z (3 months ago)
• Topics: openlane, openlane-flow, verilog, verilog-processor, verilog-project, vlsi, vlsi-design
• Language: Verilog
• Homepage:
• Size: 16.6 MB
• Stars: 8
• Watchers: 1
• Forks: 0
• Open Issues: 0

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