https://github.com/ksmashingaidze/control-unit-simulation

Microprocessor control unit simulation implemented in VHDL.
https://github.com/ksmashingaidze/control-unit-simulation

control microprocessor simulation vhdl

Last synced: 4 months ago
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Microprocessor control unit simulation implemented in VHDL.

• Host: GitHub
• URL: https://github.com/ksmashingaidze/control-unit-simulation
• Owner: ksmashingaidze
• Created: 2023-11-13T09:06:15.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2023-11-13T09:37:13.000Z (over 2 years ago)
• Last Synced: 2025-02-24T10:18:59.166Z (over 1 year ago)
• Topics: control, microprocessor, simulation, vhdl
• Language: VHDL
• Homepage:
• Size: 917 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# Control-Unit-Simulation-VHDL-

Microprocessor control unit simulation implemented in VHDL (Quartus).

This project simulates a simplified model of a Motorola CPU08 central processor unit controlled by input opcode where:

- completecontrolunit : Contains assembled control unit .bdf and Quartus project

- adder, controlunit, multitwo: Contains the individual components