Ecosyste.ms: Awesome

An open API service indexing awesome lists of open source software.

Awesome Lists | Featured Topics | Projects

https://github.com/kuangjux/kuangjux


https://github.com/kuangjux/kuangjux

Last synced: about 2 months ago
JSON representation

Awesome Lists containing this project

README

        

Hi, I'm KuangjuX šŸ‘‹

I am currently a first-year master's student at the University of Chinese Academy of Sciences. Previously, I graduated from Tianjin University with a bachelor's degree. I like system program in Rust. I am currently focusing on machine learning systems and DL compilers.
I am working on implementing a **[Dataflow Analysis and Codegen Framework](https://github.com/TiledTensor/ThrillerFlow)** and an **[Efficient Kernel Template Library](https://github.com/TiledTensor/TiledCUDA)**.
In the past, I have implemented some system projects using Rust, primarily involving operating systems and hypervisors.

Active Projects:

- [TiledCUDA](https://github.com/TiledTensor/TiledCUDA): TiledCUDA is a highly efficient kernel template library designed to elevate CUDA Cā€™s level of abstraction for processing tiles.
- [ThrillerFlow](https://github.com/TiledTensor/ThrillerFlow): ThrillerFlow is a Dataflow Analysis and Codegen Framework written in Rust.

I build operating systems in Rust:

- [xv6-rust](https://github.com/Ko-oK-OS/xv6-rust): A reimplementation of xv6-riscv rust version.
- [rCore-fat](https://github.com/KuangjuX/rCore-fat): rCore-Tutorial-v3 with fat32 file system.
- [raspberrypi-embedded/mini-game-os](https://github.com/raspberrypi-embedded/mini-game-os): A small game os run on raspverry pi 4.

I also build hypervisor(VMM) in Rust:
- [hypocaust](https://github.com/KuangjuX/hypocaust): A S mode trap and emulate type-1 hypervisor run on RISC -V machine.
- [hypocaust-2](https://github.com/KuangjuX/hypocaust-2): A hardware-assisted type-1 hypervisor with H extension run on RISC -V machine.
- [hypercraft](https://github.com/KuangjuX/hypercraft): A VMM library written in Rust.

I also build an Out-of-Order RISC-V Processor Core and difftest framework based on verilator:
- [HeliosXCore](https://github.com/HeliosXCore/HeliosXCore): A Superscalar Out-of-order RISC-V Processor Core.
- [HeliosXSimulator](https://github.com/HeliosXCore/HeliosXSimulator): A verilator-based Soc Simulator for HeliosXCore.

Some of my projects that have already been Archived are as follows:

https://github.com/KuangjuX-Archived

Others:
- [About Me](http://kuangjux.top/)
- [Curriculum Vitae](http://kuangjux.top/files/resume.pdf)