https://github.com/kyaso/bamboo

A CPU written in Verilog which implements the open RISC-V architecture.
https://github.com/kyaso/bamboo

fpga processor risc-v riscv riscv32

Last synced: 1 day ago
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A CPU written in Verilog which implements the open RISC-V architecture.

• Host: GitHub
• URL: https://github.com/kyaso/bamboo
• Owner: kyaso
• Created: 2020-07-22T21:37:30.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2020-08-13T21:58:13.000Z (over 4 years ago)
• Last Synced: 2024-11-13T18:38:10.749Z (about 1 month ago)
• Topics: fpga, processor, risc-v, riscv, riscv32
• Language: C++
• Homepage:
• Size: 37.1 KB
• Stars: 2
• Watchers: 4
• Forks: 1
• Open Issues: 1

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