https://github.com/lcq2/riscv-ida

RISC-V ISA processor module for IDAPro 7.x
https://github.com/lcq2/riscv-ida

Last synced: about 2 months ago
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RISC-V ISA processor module for IDAPro 7.x

• Host: GitHub
• URL: https://github.com/lcq2/riscv-ida
• Owner: lcq2
• License: gpl-3.0
• Created: 2018-08-20T07:45:45.000Z (about 6 years ago)
• Default Branch: master
• Last Pushed: 2020-09-05T14:52:50.000Z (about 4 years ago)
• Last Synced: 2024-04-27T04:32:11.539Z (5 months ago)
• Language: Python
• Homepage:
• Size: 38.1 KB
• Stars: 28
• Watchers: 2
• Forks: 4
• Open Issues: 3
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# RISC-V for IDA

RISC-V ISA processor module for IDA 7.x written in Python.

## Overview

**riscv-ida** is just a simple RISC-V processor module for IDA, written in Python for best compatibility across platforms and to ease the development process.

Albeit very simple in nature, the plugin is already quite useful, allowing for instruction simplification, basic emulation and cross-references.

The main reason I decided to write a RISC-V module for IDA is that I'm working on a RISC-V emulator/virtual-machine project, and since I'm new to RISC-V, the best way to start is writing a disassembler, to get a feeling of the architecture.

## Install

Just copy riscv.py into *procs* folder of IDA. Start ida.exe and not ida64.exe, 64bit support is still missing (coming soon).

## Use

You need to manually choose RISC-V in the cpu selector when you load a binary. ELF loader support coming soon...

## Missing

Too much... :D

Soon to come:

- 64bit support in IDA

- Data cross reference

- Better emu

- Better integration with ELF loader (no more Unrecognized cpu blabla)

Someday:

- Stack tracing (very nice to have...)

- 128bit?

# License

GPLv3