https://github.com/leecannon/zriscv

RISC-V emulator in Zig
https://github.com/leecannon/zriscv

risc-v riscv zig ziglang

Last synced: 29 days ago
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RISC-V emulator in Zig

• Host: GitHub
• URL: https://github.com/leecannon/zriscv
• Owner: leecannon
• License: mit
• Archived: true
• Created: 2021-07-01T13:32:04.000Z (over 3 years ago)
• Default Branch: master
• Last Pushed: 2023-11-04T00:26:52.000Z (about 1 year ago)
• Last Synced: 2024-08-03T23:24:15.674Z (4 months ago)
• Topics: risc-v, riscv, zig, ziglang
• Language: Zig
• Homepage:
• Size: 536 KB
• Stars: 15
• Watchers: 4
• Forks: 0
• Open Issues: 3
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-zig - leecannon/zriscv - V emulator in Zig. (Emulators / Zigged Project)

README

        
# zriscv

[![CI](https://github.com/leecannon/zriscv/actions/workflows/main.yml/badge.svg?branch=master)](https://github.com/leecannon/zriscv/actions/workflows/main.yml)

RISC-V emulator in Zig

## What to expect

This is the first emulator I've made other than CHIP-8, don't expect high quality nor speed.

The only thing that should be expected is mistakes.

The focus is on correctness not performance, I'm expecting practically every execution path to be littered with potential optimization opportunities.

## Goal

 - RV64GC

 - user, super and machine mode

 - provide a linux userspace emulation similar to qemu's

## Progress

- [X] RV64I (64-bit Base Integer)

- [ ] M (Multiplication and Division)

- [ ] A (Atomic)

- [ ] F (Single-Precision Floating-Point)

- [ ] D (Double-Precision Floating-Point)

- [ ] Zicsr (Control and Status Register)

- [ ] Zifencei (Instruction-Fetch Fence)

- [ ] C (Compressed Instructions)

- [ ] Counters

- [ ] Machine-Level ISA

- [ ] Supervisor-Level ISA

- [ ] CSRs

## Spec

The version of the riscv spec used is draft-20220831-bf5a151 released 31/08/2022