https://github.com/lemongrb/digitaldesignwithverilog

Simple circuits designed with verilog
https://github.com/lemongrb/digitaldesignwithverilog

asic behavioural dataflow design digitalsystems fpga structural verilog verilog-code verilog-project verilogprojects

Last synced: about 3 hours ago
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Simple circuits designed with verilog

• Host: GitHub
• URL: https://github.com/lemongrb/digitaldesignwithverilog
• Owner: lemongrb
• Created: 2024-11-09T10:23:31.000Z (2 months ago)
• Default Branch: main
• Last Pushed: 2024-12-03T15:40:31.000Z (about 1 month ago)
• Last Synced: 2025-01-02T17:44:08.546Z (8 days ago)
• Topics: asic, behavioural, dataflow, design, digitalsystems, fpga, structural, verilog, verilog-code, verilog-project, verilogprojects
• Language: Verilog
• Homepage:
• Size: 11.7 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
### DIGITAL DESIGN WITH VERILOG :

#### 1)-A brief overview about verilog : 

Verilog is a hardware description language used to model digital circuits.

Verilog supports three modelling styles that allow you to design different circuits with different philosophie(behavrioural, structural and dataflow).

Verilog has similar C-syntax and Verilog is a concurrent language, different than a “procedural” language like C or Java(statements are executed in parallel).

#### 2)-Tools and Simulators : 

ModelSim and Quartus prime are used to test and verify and simulate HDL codes(they support systemVerilog, VHDL, systemC ...).