https://github.com/lemongrb/sequencedetector

11001 sequence detector
https://github.com/lemongrb/sequencedetector

asic digital-design fpga hardware hardware-description-language hdl sequence-detection sequence-detector verilog

Last synced: 15 days ago
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11001 sequence detector

• Host: GitHub
• URL: https://github.com/lemongrb/sequencedetector
• Owner: lemongrb
• Created: 2024-12-04T09:56:10.000Z (about 2 months ago)
• Default Branch: main
• Last Pushed: 2024-12-04T10:19:15.000Z (about 2 months ago)
• Last Synced: 2025-01-02T17:44:08.829Z (23 days ago)
• Topics: asic, digital-design, fpga, hardware, hardware-description-language, hdl, sequence-detection, sequence-detector, verilog
• Language: Verilog
• Homepage:
• Size: 8.79 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
This is an overlapping sequence detector implemented using verilog language.

#### State Table : 

  

   Current State

   Next State(in = 0, in = 1)

   Output(in = 0, in = 1)  

  

     S0 

    S0, S1

    0, 0

  

  

     S1 

    S0, S2

    0, 0

    

  

     S2 

    S3, S2

    0, 0

  

  

     S3 

    S4, S2

    0, 0

  

  

     S4 

    S0, S1

    0, 1