https://github.com/leobel96/polito-sdi-reflexesanalyzer

Teamwork project of a reflexes analyzer made during the course "Sistemi Digitali Integrati" (Integrated Digital Systems) @ Politecnico di Torino
https://github.com/leobel96/polito-sdi-reflexesanalyzer

digital-electronics fpga integrated-circuits modelsim quartus vhdl

Last synced: 19 days ago
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Teamwork project of a reflexes analyzer made during the course "Sistemi Digitali Integrati" (Integrated Digital Systems) @ Politecnico di Torino

• Host: GitHub
• URL: https://github.com/leobel96/polito-sdi-reflexesanalyzer
• Owner: leobel96
• Created: 2019-11-20T21:55:00.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2019-11-20T22:03:14.000Z (about 5 years ago)
• Last Synced: 2023-07-13T15:47:03.558Z (over 1 year ago)
• Topics: digital-electronics, fpga, integrated-circuits, modelsim, quartus, vhdl
• Language: VHDL
• Size: 10 MB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:

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