https://github.com/leonrinkel/lake

Yet another RISC-V core implemented in Verilog
https://github.com/leonrinkel/lake

Last synced: 4 months ago
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Yet another RISC-V core implemented in Verilog

• Host: GitHub
• URL: https://github.com/leonrinkel/lake
• Owner: leonrinkel
• Created: 2022-10-01T14:37:44.000Z (almost 4 years ago)
• Default Branch: main
• Last Pushed: 2022-10-02T08:16:27.000Z (almost 4 years ago)
• Last Synced: 2025-02-26T17:48:31.470Z (over 1 year ago)
• Language: Verilog
• Size: 14.6 KB
• Stars: 1
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          
# lake

Yet another RISC-V core implemented in Verilog

```sh

$ ./cc.sh # compile prog.c

$ mkdir build && cd build

$ cmake .. # configure project

$ make # build project

$ ./lake_test # run simulation

```