https://github.com/lethalbit/yosys-vscode

Syntax Highlighting for Yosys Scripts and RTLIL
https://github.com/lethalbit/yosys-vscode

eda fpga rtlil syntax-highlighting vscode-extension yosys

Last synced: 3 months ago
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Syntax Highlighting for Yosys Scripts and RTLIL

• Host: GitHub
• URL: https://github.com/lethalbit/yosys-vscode
• Owner: lethalbit
• License: bsd-3-clause
• Created: 2023-02-24T16:39:45.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2023-04-18T17:19:16.000Z (about 2 years ago)
• Last Synced: 2025-03-22T12:11:55.781Z (3 months ago)
• Topics: eda, fpga, rtlil, syntax-highlighting, vscode-extension, yosys
• Homepage:
• Size: 341 KB
• Stars: 5
• Watchers: 3
• Forks: 0
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE
  • Code of conduct: CODE_OF_CONDUCT.md

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README

        
# Yosys + RTLIL Syntax Highlighting

This VSCode extension adds syntax highlighting support for [Yosys](https://github.com/YosysHQ/yosys). Adding both RTLIL and Yosys script support.

![A screenshot of a Yosys script showing a verilog heredoc](./_images/yosys-script.png)

![A screenshot of some RTLIL](./_images/rtlil.png)

## License

This VSCode extension is licensed under the [BSD-3-Clause](https://spdx.org/licenses/BSD-3-Clause.html) license, the full text of which can be found in the [`LICENSE`](./LICENSE) file.