https://github.com/lichtso/riscv-llvm-templates
Code templates to get started experimenting with the RISC-V LLVM toolchain
https://github.com/lichtso/riscv-llvm-templates
code-templates llvm risc-v riscv
Last synced: about 1 year ago
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Code templates to get started experimenting with the RISC-V LLVM toolchain
- Host: GitHub
- URL: https://github.com/lichtso/riscv-llvm-templates
- Owner: Lichtso
- License: mit
- Created: 2018-11-22T15:49:28.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2018-11-25T08:39:47.000Z (over 7 years ago)
- Last Synced: 2025-03-26T11:21:14.544Z (about 1 year ago)
- Topics: code-templates, llvm, risc-v, riscv
- Language: C
- Homepage:
- Size: 4.88 KB
- Stars: 13
- Watchers: 4
- Forks: 2
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# RISC-V LLVM Templates
This repo is similar to [riscv-probe](https://github.com/michaeljclark/riscv-probe) but utilizes the LLVM toolchain instead of the GNU toolchain.
## Contains
- Makefile
- LLVM invocations
- Linker Script
- Virtual memory map
- Layout of the executable
- Assembly
- Setting the stack pointer
- Calling main()
- Calling exit()
- C
- Minimal host / target interface
- Classical "Hello World!"
## Usage
Set the LLVM and RISCV environment variables if you haven't installed the prerequisites at their defaults.
- `make` to build all targets
- `make clean` to delete all targets
- To show the targets disassembly, sections, symbols, etc:
- `make dump.spike`
- `make dump.rv8`
- To run it:
- `make run.spike`
- `make run.qemu`
- `make run.rv8`
## Prerequisites
You will need this repo, the llvm toolchain compiled with the experimental RISC-V target and at least one of the three simulators / emulators listed below.
### LLVM
```
git clone https://git.llvm.org/git/llvm.git
cd llvm/tools
git clone https://git.llvm.org/git/clang.git
git clone https://git.llvm.org/git/lld.git
cd ../..
mv llvm llvmSrc
mkdir llvm
cd llvm
cmake -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD="RISCV" -DLLVM_LINK_LLVM_DYLIB=ON ../llvmSrc/
make -j8 clang llc lld llvm-objdump llvm-readobj
```
### Simulators / Emulators
- Spike
- [device tree compiler](https://github.com/dgibson/dtc)
- [frontend server](https://github.com/riscv/riscv-fesvr)
- [isa simulator](https://github.com/riscv/riscv-isa-sim)
- [qemu](https://github.com/riscv/riscv-qemu.git)
- [rv8](https://github.com/rv8-io/rv8)