https://github.com/logisim-evolution/logisim-evolution

Digital logic design tool and simulator
https://github.com/logisim-evolution/logisim-evolution

circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl

Last synced: about 1 month ago
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Digital logic design tool and simulator

• Host: GitHub
• URL: https://github.com/logisim-evolution/logisim-evolution
• Owner: logisim-evolution
• License: gpl-3.0
• Created: 2014-09-19T05:23:24.000Z (almost 10 years ago)
• Default Branch: main
• Last Pushed: 2024-04-03T06:01:43.000Z (5 months ago)
• Last Synced: 2024-04-03T07:23:23.897Z (5 months ago)
• Topics: circuit, circuits, digital-circuit, digital-circuits, digital-logic, digital-logic-design, education, fpga, logic, logisim, logisim-evolution, simulator, timing-diagram, verilog, vhdl
• Language: Java
• Homepage:
• Size: 105 MB
• Stars: 4,252
• Watchers: 64
• Forks: 563
• Open Issues: 220
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGES.md
  • Contributing: .github/CONTRIBUTING.md
  • License: LICENSE.md
  • Citation: CITATION.cff
  • Codeowners: .github/CODEOWNERS
  • Security: .github/SECURITY.md
  • Support: support/Flatpak/README.md

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