https://github.com/lordofhyphens/xilinx-spi

Xilinx FPGA-based Serial Periphial Interface Bus implementation in VHDL.
https://github.com/lordofhyphens/xilinx-spi

Last synced: 3 months ago
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Xilinx FPGA-based Serial Periphial Interface Bus implementation in VHDL.

• Host: GitHub
• URL: https://github.com/lordofhyphens/xilinx-spi
• Owner: lordofhyphens
• Created: 2009-04-24T22:05:00.000Z (about 16 years ago)
• Default Branch: master
• Last Pushed: 2009-04-25T15:27:01.000Z (about 16 years ago)
• Last Synced: 2025-01-28T17:49:23.506Z (4 months ago)
• Homepage:
• Size: 85 KB
• Stars: 2
• Watchers: 2
• Forks: 0
• Open Issues: 0

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