https://github.com/losfair/magicore

An out-of-order processor that supports multiple instruction sets.
https://github.com/losfair/magicore

cpu risc-v riscv

Last synced: 3 months ago
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An out-of-order processor that supports multiple instruction sets.

• Host: GitHub
• URL: https://github.com/losfair/magicore
• Owner: losfair
• Created: 2022-04-10T09:44:57.000Z (over 2 years ago)
• Default Branch: master
• Last Pushed: 2022-08-23T18:10:46.000Z (over 2 years ago)
• Last Synced: 2023-08-07T22:41:05.883Z (over 1 year ago)
• Topics: cpu, risc-v, riscv
• Language: Scala
• Homepage:
• Size: 491 KB
• Stars: 17
• Watchers: 5
• Forks: 2
• Open Issues: 2
• Metadata Files:
  • Readme: README.md

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README

        
# MagiCore

An out-of-order processor that supports multiple instruction sets. My playground for experimenting with new microarchitecture & ISA ideas.

![Architecture](res/arch.svg)

## ISA support status

- [x] RISC-V RV32IMAU

- [x] RISC-V RV64IMAU

- [ ] eBPF

- [ ] MIPS

## Performance

Currently MagiCore's frontend (IFetch/Decode) is not superscalar so the performance is limited to <1 IPC. 2.27 CoreMark/MHz, ~106MHz on Artix 7.