https://github.com/lowrisc/lowrisc-artya7

Port of lowrisc to low cost artya7-100 FPGA
https://github.com/lowrisc/lowrisc-artya7

Last synced: about 1 month ago
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Port of lowrisc to low cost artya7-100 FPGA

• Host: GitHub
• URL: https://github.com/lowrisc/lowrisc-artya7
• Owner: lowRISC
• License: other
• Created: 2018-07-16T15:55:40.000Z (almost 8 years ago)
• Default Branch: refresh-v0.6
• Last Pushed: 2018-07-20T08:20:10.000Z (almost 8 years ago)
• Last Synced: 2025-01-20T06:42:56.712Z (over 1 year ago)
• Language: Makefile
• Size: 939 KB
• Stars: 1
• Watchers: 9
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

          
lowRISC Digilent NEXYS4-DDR Board Developement Demo

========================================================

(Not a stand-alone git repo. Please clone https://github.com/lowrisc/lowrisc-chip.git to have this as a submodule of /fpga/board/nexys4)

Requirement:

  **Vivado 2015.4** and **lowRISC develope environment**

How to run the demo:

--------------------------------------------------------

* Generate bit-stream for downloading

        make bitstream

* Run FPGA simulation (extremely slow due to the DDR3 memory controller)

        make simulation

* Open the Vivado GUI

        make vivado

Other Make targets

--------------------------------------------------------

* Generate the FPGA backend Verilog files

        make verilog

* Generate the Vivado project

        make project

* Find out the boot BRAMs' name and position (for updating src/boot.bmm)

        make search-ramb

* Replace the content of boot BRAM with a new src/boot.mem (must update src/boot.bmm first)

        make bit-update