https://github.com/lowrisc/lowrisc-nexys4

FPGA demo for Digilent NEXYS 4 board
https://github.com/lowrisc/lowrisc-nexys4

Last synced: 1 day ago
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FPGA demo for Digilent NEXYS 4 board

• Host: GitHub
• URL: https://github.com/lowrisc/lowrisc-nexys4
• Owner: lowRISC
• License: other
• Created: 2015-11-25T15:47:25.000Z (almost 9 years ago)
• Default Branch: master
• Last Pushed: 2019-10-02T12:51:31.000Z (about 5 years ago)
• Last Synced: 2024-08-10T14:21:32.994Z (3 months ago)
• Language: Tcl
• Size: 1.96 MB
• Stars: 22
• Watchers: 10
• Forks: 15
• Open Issues: 4
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
lowRISC Digilent NEXYS4-DDR Board Developement Demo

========================================================

(Not a stand-alone git repo. Please clone https://github.com/lowrisc/lowrisc-chip.git to have this as a submodule of /fpga/board/nexys4)

Requirement:

  **Vivado 2015.4** and **lowRISC develope environment**

How to run the demo:

--------------------------------------------------------

* Generate bit-stream for downloading

        make bitstream

* Run FPGA simulation (extremely slow due to the DDR3 memory controller)

        make simulation

* Open the Vivado GUI

        make vivado

Other Make targets

--------------------------------------------------------

* Generate the FPGA backend Verilog files

        make verilog

* Generate the Vivado project

        make project

* Find out the boot BRAMs' name and position (for updating src/boot.bmm)

        make search-ramb

* Replace the content of boot BRAM with a new src/boot.mem (must update src/boot.bmm first)

        make bit-update