https://github.com/lsc-unicamp/processor-ci-controller

Controller module for RISC-V core CI/CD
https://github.com/lsc-unicamp/processor-ci-controller

fpga riscv verilog

Last synced: about 20 hours ago
JSON representation

Controller module for RISC-V core CI/CD

• Host: GitHub
• URL: https://github.com/lsc-unicamp/processor-ci-controller
• Owner: LSC-Unicamp
• License: cern-ohl-p-2.0
• Created: 2024-02-17T23:49:59.000Z (9 months ago)
• Default Branch: main
• Last Pushed: 2024-09-14T17:41:59.000Z (2 months ago)
• Last Synced: 2024-09-15T03:22:49.235Z (2 months ago)
• Topics: fpga, riscv, verilog
• Language: Verilog
• Homepage: https://lsc-unicamp.github.io/processor-ci-controller/
• Size: 2.26 MB
• Stars: 8
• Watchers: 1
• Forks: 0
• Open Issues: 3
• Metadata Files:
  • Readme: README.md
  • Contributing: CONTRIBUTING.md
  • License: LICENSE

Awesome Lists containing this project

README

        
# Hardware infrastructure

## Processor CI Controller

Processor CI Controller is a hardware module that acts as a wrapper around the processor core, enabling control over it, monitoring the memory bus, and managing signals such as clock, reset, and halt.

## Project Modules

The controller is divided into various modules, each responsible for performing a specific function. Among the existing modules, the main ones are:

![Diagram with the modules](docs/img/controlador-riscv.svg)

### Interpreter

The interpreter is responsible for receiving instructions sent by the test software and issuing commands to other modules. These commands can involve tasks such as reading and writing to memory, providing N clock cycles to the processor, etc.

### Communication Module

The communication module acts as the bridge between the host machine running the test software and the controller. It is responsible for implementing the protocol to be used, which could be UART, SPI, or PCIe.

### Clock Controller

The clock controller manages the clock signal provided to the processor. It has the capability to supply a specific number of pulses and/or divide the clock frequency.

### Memory Controller

The memory controller provides an access interface to the memory for both the controller and the processor, managing the priority with which each can interact with the memory.

## Currently supported FPGAs Boards

- Digilent Nexys 4 DDR

- Tang nano 20k

- Colorlight i9

- Digilent Arty A7 100T

- Xilinx VC709

- Cyclone 10 GX (In progress)